
// Copyright (c) 2012, <OWNER>
// All rights reserved.
// 
// Redistribution and use in source and binary forms, with or without
// modification, are permitted provided that the following conditions are met: 
// 
// 1. Redistributions of source code must retain the above copyright notice, this
//    list of conditions and the following disclaimer. 
// 2. Redistributions in binary form must reproduce the above copyright notice,
//    this list of conditions and the following disclaimer in the documentation
//    and/or other materials provided with the distribution. 
// 
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
// ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
// WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
// DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR
// ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
// LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
// ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
// SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
// 
// The views and conclusions contained in the software and documentation are those
// of the authors and should not be interpreted as representing official policies, 
// either expressed or implied, of the FreeBSD Project.
// 
// 
#define APTIO
#include "snb.h"

#define PCIE_CFG_ADDR(bus,dev,func,reg) \
	  ((VOID*) (UINTN)(PCIEX_BASE_ADDRESS + ((bus) << 20) + ((dev) << 15) + ((func) << 12) + reg))

// Utility.
// To read TDP of CPU via CSR/MSR
// FIXME: MSR for DT processor.
uint64_t read_tdp(uint8_t node)
{
	uint64_t* addr;
	package_power_sku* power_sku;
	package_power_sku_unit* unit;

	addr = PCIE_CFG_ADDR(0xff, 10, 0, 0x84);
	power_sku = (package_power_sku*)addr;
	addr = PCIE_CFG_ADDR(0xff, 10, 0, 0x8C);
	unit = (package_power_sku_unit*)addr;

	return power_sku->package_tdp_power >> unit->power_unit;
}

uint64_t nr_cpu = 0; 

static init_cpu_info(void)
{
	nr_cpu = (*(uint32_t*)PCIE_CFG_ADDR(0x80, 0, 0, 0) == -1) ? 1: 2;
}

uint64_t read_dimmtemp(uint8_t node, uint8_t ch_idx)
{
    uint32_t v;
    uint8_t uncore_bus;
    if (nr_cpu == 0)
        init_cpu_info();

    if (nr_cpu == 1) {
        uncore_bus = 0xff;
    } else if (nr_cpu == 2) {
        uncore_bus = (node == 0)? 0x7f: 0xff;
    }
    v = *(uint32_t*)(PCIE_CFG_ADDR(uncore_bus, 15, 0, 0x120)) ;
    if (ch_idx == 0) {
        if (v & (1 << 15)) 
            return  v & 0xff;
        else
            return -1; 
    } else if (ch_idx == 1) {
        if (v & (1 << 31)) 
            return  (v>>16) & 0xff;
        else
            return -1;
    }
    return -1;
}


